Devices Included in this Data Sheet: PIC16FA K .. You can determine the version of a data sheet by examining its literature number found on the. IC datasheet. PIC16FA datasheet specifies that this CMOS FLASH-based 8-bit microcontroller packs Microchip’s powerful PIC architecture into an or pin package and is upwards compatible with the PIC16C5X, PIC12CXXX and PIC16C7X devices. download PIC16FA datasheet. Learn about PIC16FA PIC series microcontroller with its a detailed overview of PIC16FA features with its PDF datasheet to download.

Pic16f877a Datasheet Pdf

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Microcontrollers. PDF created with pdfFactory trial version spicesinlaris.ml . PIC16FA K. .. To obtain the most uputoudate version of this data sheet, please register at our Worldwide Web site at. PIC16FA datasheet, PIC16FA circuit, PIC16FA data sheet: MICROCHIP - 28/pin Enhanced FLASH Microcontrollers,alldatasheet, datasheet. PIC16F Datasheet PDF Download - PIC16F87X 28/Pin 8-Bit CMOS FLASH Microcontrollers Devices Included in this Data Sheet: • PIC16F

The destination and one of the sources also support addressing modes, allowing the operand to be in memory pointed to by a W register. A small number of fixed-length instructions Most instructions are single-cycle 2 clock cycles, or 4 clock cycles in 8-bit models , with one delay cycle on branches and skips One accumulator W0 , the use of which as source operand is implied i.

There is no distinction between memory space and register space because the RAM serves the job of both memory and registers, and the RAM is usually just referred to as the register file or simply as the registers.

Special-purpose control registers for on-chip hardware resources are also mapped into the data space.

The addressability of memory varies depending on device series, and all PIC devices have some banking mechanism to extend addressing to additional memory.

Later series of devices feature move instructions, which can cover the whole addressable space, independent of the selected bank. In earlier devices, any register move had to be achieved through the accumulator. External data memory is not directly addressable except in some PIC18 devices with high pin count. In general, there is no provision for storing code in external memory due to the lack of an external memory interface.

However, the unit of addressability of the code space is not generally the same as the data space. In contrast, in the PIC18 series, the program memory is addressed in 8-bit increments bytes , which differs from the instruction width of 16 bits.

In order to be clear, the program memory capacity is usually stated in number of single-word instructions, rather than in bytes. Stacks[ edit ] PICs have a hardware call stack , which is used to save return addresses. The hardware stack is not software-accessible on earlier devices, but this changed with the 18 series devices. Hardware support for a general-purpose parameter stack was lacking in early series, but this greatly improved in the 18 series, making the 18 series architecture more friendly to high-level language compilers.

The instruction set includes instructions to perform a variety of operations on registers directly, the accumulator and a literal constant or the accumulator and a register , as well as for conditional execution, and program branching. Some operations, such as bit setting and testing, can be performed on any numbered register, but bi-operand arithmetic operations always involve W the accumulator , writing the result back to either W or the other operand register.

To load a constant, it is necessary to load it into W before it can be moved into another register. Shrivastava, A. Verma, and S. He, and J. Jang, S. Shin, J. Lee, and S. Chang, C. Chang, and Y. Tarulescu, S. Data Sheet and Product Features. Elec Freaks.

PDF PIC16F874A Datasheet ( Hoja de datos )

Start and Stop conditions indicate the beginning The MSSP module generates an interrupt at the and end of transmission. Section 9. Interrupt is generated once the Stop condition is complete. The BRG counts down to 0 and stops instruction cycles and the BRG value loaded into until another reload has taken place.

The I2Cinterface does not conform to the kHz I2C specification which applies to rates greater than kHz in all details, but may be used with care where higher rates are required by the application. When the. BRG decrements on Q2 and Q4 cycles. BRG 03h 02h 01h 00h hold off 03h 02h Value. SDA pin is driven low. When the SCL pin is sam- mode. SDA Note: Following Start condition is complete. If RSEN is programmed while any other event is in progress, it will not take effect. A bus collision during the Repeated Start condition occurs if: A slave sends an Acknowledge when set the Buffer Full flag bit, BF, and allow the Baud Rate it has recognized its address including a general call Generator to begin counting and start the next trans- or when the slave has properly received its data.

Data should be valid before SCL is released high see data setup time specification, Note: The data on the SDA pin will be disregarded. The MSSP the falling edge of the ninth clock. If the master receives is now in Idle state, awaiting the next command.

If not, the bit is set. After the ninth ically cleared. The status of the ACK bit is already set from a previous reception.

Following the falling edge of the ninth clock transmis- 9. WCOL must be cleared in software.

Start transmit. After Start condition, SEN cleared by hardware. When this bit is set, the SCL pin is transmit, the SCL line is held low after the falling edge pulled low and the contents of the Acknowledge data bit of the ninth clock.

PIC16F877A PDF – Microcontrollers – Microchip

If the user wishes to gen- will assert the SDA line low. When the Baud Rate Generator starting an Acknowledge sequence. When the SDA pin will be deasserted.

The SCL pin is then set. When the SCL pin floats current transfer. When the user services the bus is Idle, with both the S and P bits clear. When the bus collision Interrupt Service Routine and if the I2C bus is busy, enabling the SSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs.

In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge condition monitored for arbitration to see if the signal level is at was in progress when the bus collision occurred, the con- the expected output level.

In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determi- nation of when the bus is free.

Bus collision has occurred. SDA released by master. At the Figure The reason that bus collision is not a factor pins are monitored. Therefore, one master will always assert SDA before the other.

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SDA sampled low before Start condition. At the end of the count, counts down to 0. Interrupt cleared in software RSEN.

When the pin is sampled high clock arbitration , Bus collision occurs during a Stop condition if: Communications Interface or SCI. The USART can be configured as a full-duplex asynchronous system that The USART module also has a multi-processor can communicate with peripheral devices, such as communication capability using 9-bit address detection. Clock Source Select bit Asynchronous mode: Synchronous mode: High Baud Rate Select bit Asynchronous mode: Single Receive Enable bit Asynchronous mode: Synchronous mode — Master: Synchronous mode — Slave: Continuous Receive Enable bit Asynchronous mode: This ensures the period of a free running 8-bit timer.

Table shows the formula for computation of the From this, the error in baud rate can be determined. Shaded cells are not used by the BRG. It will reset only when new data is loaded into the bits and one Stop bit. While flag bit TXIF indicates the status is 8 bits. Status bit TRMT frequencies from the oscillator. The transmitter and receiver empty. No interrupt logic is tied to this bit so the user are functionally independent but use the same data has to poll this bit in order to determine if the TSR format and baud rate.

The baud rate generator register is empty.

Parity is not Note 1: The TSR register is not mapped in data supported by the hardware but can be implemented in memory so it is not available to the user. The heart of the transmitter is the Transmit to high-impedance. The ninth bit must be been transmitted from the previous load. This interrupt can be register. Enable the transmission by setting bit TXEN, follow these steps: If 9-bit transmission is selected, the ninth bit baud rate.

If a high-speed baud rate is desired, should be loaded in bit TX9D. Enable the asynchronous serial port by clearing 8. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set transmit bit TX9. Empty Flag. Transmit Shift Reg. Shaded cells are not used for asynchronous transmission. On the detection of The receiver block diagram is shown in Figure The data recovery block is be set.

The word in the RSR will be lost. The RCREG actually a high-speed shifter, operating at x16 times the register can be read twice to retrieve the two bytes in baud rate; whereas the main receive serial shifter the FIFO.

This is done by resetting the receive logic CREN Once Asynchronous mode is selected, reception is is cleared and then set. It is, therefore, Register RSR.

If the transfer is complete, flag detected as clear. The actual interrupt can be buffered the same way as the receive data. Flag bit RCIF is a read-only bit which is values, therefore, it is essential for the user to read the cleared by the hardware. This timing diagram shows three words appearing on the RX input.

When setting up an Asynchronous Reception, follow 6. Flag bit RCIF will be set when reception is com- these steps: If a high-speed baud rate is desired, 7. RCREG register. If interrupts are desired, then set enable bit 9. If any error occurred, clear the error by clearing RCIE. If 9-bit reception is desired, then set bit RX9.

Enable the reception by setting bit CREN. Shaded cells are not used for asynchronous reception. When setting up an Asynchronous Reception with address detect enabled: This timing diagram shows a data byte followed by an address byte. When transmitting data, pin reverts to a high-impedance state for a reception. In internal clock. The If bit SREN is set to interrupt an on-going transmission Master mode indicates that the processor transmits the and receive a single word , then after the single word is master clock on the CK line.

The DT line will immediately switch from High- The TSR register is not loaded until the last result in an immediate transfer of the data to the TSR bit has been transmitted from the previous load. As register if the TSR is empty.

It will reset only when new data is loaded into the 2. If interrupts are desired, set enable bit TXIE. TRMT is a read- 4. If 9-bit transmission is desired, set bit TX9. No inter- 5. Enable the transmission by setting bit TXEN. The 6. If 9-bit transmission is selected, the ninth bit TSR is not mapped in data memory so it is not available should be loaded in bit TX9D.

The actual transmission will not occur 8. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock Figure Back-to-back transfers are possible. Shaded cells are not used for synchronous master transmission.

Data When setting up a Synchronous Master Reception: If both bits are 2. Enable the synchronous master serial port by set, CREN takes precedence. When the transfer is complete, interrupt flag bit, RCIF 4.

Flag bit RCIF is a read-only bit which is 6. If a single reception is required, set bit SREN. RCREG register has been read and is empty. The 7. It is possible for two bytes of data to be enable bit RCIE was set. On the enabled and determine if any error occurred clocking of the last bit of the third byte, if the RCREG during reception.

Bit OERR has to be cleared in If any error occurred, clear the error by clearing software by clearing bit CREN. Shaded cells are not used for synchronous master reception.

Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at 1. This allows the device to transfer or CSRC. Slave mode is 2. If 9-bit transmission is desired, then set bit TX9. SLEEP instruction is executed, the following will occur: TSR register and transmit. Shaded cells are not used for synchronous slave transmission. The operation of the Synchronous Master and Slave 1.

If receive is enabled by setting bit CREN prior to the 2. If interrupts are desired, set enable bit RCIE. SLEEP instruction, then a word may be received during 3. If 9-bit reception is desired, set bit RX9. On completely receiving the word, the RSR reg- 4. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is enable bit RCIE bit is set, the interrupt generated will complete and an interrupt will be generated if wake the chip from Sleep.

If the global interrupt is enable bit RCIE was set. If any error occurred, clear the error by clearing bit CREN.

Shaded cells are not used for synchronous slave reception. These registers are: The port pins can be configured or RA3. Reference Manual DS Do not select any unimplemented channels with these devices. On any device Reset, the port pins that are multiplexed with analog functions ANx are forced to be an analog input.

Wait the required acquisition time. Start conversion: To determine sample time, see Section The To calculate the minimum acquisition time, analog input model is shown in Figure The source Equation may be used.

The sampling switch to meet its specified resolution. As the Manual DS The reference voltage VREF has no effect on the equation since it cancels itself out. The maximum recommended impedance for analog sources is 2. This is required to meet the pin leakage specification. If the TRIS bit is cleared output , the digital software selected.

AN0 of 1. TAD vs. For extended voltage devices LF , please refer to Section This register pair is 16 bits wide. Right Justified Left Justified. To allow the con- ADCS1: When the conver- These registers are not available on pin devices. A block diagram The comparator module contains two analog compara- of the various comparator configurations is shown in tors.

The inputs to the comparators are multiplexed Figure The on-chip volt- age reference Section CM0 bit settings.

Figure shows the eight possible modes. If the Comparator Otherwise, a false interrupt may occur. Section In this the output of the comparator in Figure represent mode, the internal voltage reference is applied to the the uncertainty due to input offsets and response time. The new reference voltage or input source, before the com- analog signal present at VIN- is compared to the signal parator output has a valid level. Otherwise, the maximum delay of the comparators should be used Section These bits are read-only.

When enabled, multiplexors in the output path of the RA4 and RA5 pins will switch and the output of each pin will be the unsynchronized output of the com- parator. Figure shows the comparator output block diagram. When reading the Port register, all pins Pins configured as digital inputs will comparator module can be configured to have the com- convert an analog input according to the parators operate from the same or different reference Schmitt Trigger input specification.

However, threshold detector applications may 2: Analog levels on any pin defined as a dig- require the same reference. The reference signal must ital input may cause the input buffer to be between VSS and VDD and can be applied to either consume more current than is specified. When used as an output, a pull-up resistor is required. The interrupt in the following manner: If any of these bits are allow flag bit CMIF to be cleared.

Since the analog pins are connected to a interrupt is functional if enabled. This interrupt will digital output, they have reverse biased diodes to VDD wake-up the device from Sleep mode when enabled.

If the input voltage deviates from this currents than shown in the power-down current range by more than 0. Each operational comparator diodes is forward biased and a latch-up condition may will consume additional current as shown in the com- occur. To minimize power consumption ommended for the analog sources.

Shaded cells are unused by the comparator module. A programmable register controls the function of The output of the reference generator may be con- the reference generator. The primary purpose of this mented to provide two ranges of CVREF values and has function is to provide a test path for testing the a power-down function to conserve power when the reference generator function.

The comparator reference. Shaded cells are not used with the comparator voltage reference. The RC oscillator power saving operating modes and offer code option saves system cost while the LP crystal option protection. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. It is designed to keep the part in Reset while the power supply stabilizes. With these two timers on-chip, most applications need no external Reset circuitry.

Use of a series cut crystal may give a frequency out 2. When in 4. See Table and Table for recommended values of C1 and C2. A series resistor Rs may be required for AT strip cut crystals.

RF varies with the crystal chosen. Range Cap. Range option offers additional cost savings. In addition to this, the oscillator kHz 15 pF 15 pF frequency will vary from unit to unit due to normal pro- XT kHz pF pF cess parameter variation.

Higher capacitance increases the stability of oscillator but also increases the start-up time. Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. They are not affected by a WDT of Reset: Some registers are not affected in any Reset condition.

Their status is unknown on POR and unchanged in any other Reset. Enable PWRT. Enable OST. The filter will detect and ignore small time-out on power-up only from the POR. The Power- pulses. The MCLR pin low. Voltages applied to the pin that exceed its specification can The power-up time delay will vary from chip to chip due result in both Resets and current consumption outside to VDD, temperature and process variation. See of device specification during the Reset event. For this Section The use of an RCR network, as shown in Figure , is suggested.

MCLR R2 2 Once the brown-out occurs, the device will remain in 2: The Power-up Timer is always enabled when the Brown-out Reset circuit is To take A maximum rise time for VDD is specified. Then, OST starts counting oscillator details. Reset condition , device operating parameters volt- If MCLR is kept low long enough, the time-outs will age, frequency, temperature, etc.

Bringing MCLR high will begin execution ensure operation. If these conditions are not met, the immediately. This is useful for testing purposes or to device must be held in Reset until the operating condi- synchronize more than one PIC16F87XA device tions are met. Brown-out Reset may be used to meet operating in parallel. Reset conditions for all the registers. It is two bits depending upon the device. The BOR wise.

The user must set this bit following a Power-on bit is unknown on a Power-on Reset.

It must then be set Reset. When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector h. Shaded cells indicate conditions do not apply for the designated device. See Table for Reset value for specific condition. CASE 1. It also The peripheral interrupt flags are contained in the has individual and global interrupt enable bits. The corresponding interrupt enable bits are contained in Note: Once in the Interrupt Service Routine, the vector immediately.

Individual interrupts can be source s of the interrupt can be determined by polling disabled through their corresponding enable bits in the interrupt flag bits. The interrupt flag bit s must be various registers. Individual interrupt bits are set cleared in software before re-enabling interrupts to regardless of the status of the GIE bit. The GIE bit is avoid recursive interrupts. The exact latency re-enables interrupts. The latency is the same for one or two-cycle instructions. When a valid edge isters during an interrupt i.

This will have to be implemented in software. The INT must be defined at the same offset from the bank base interrupt can wake-up the processor from Sleep if bit address i. The status of it must also be defined at 0xA0 in Bank 1. See Section The interrupt can be text save and restore. See Section 5. See Section 4.

 2003 Microchip Technology Inc. DS39582B

ISR ; Insert user code here: Values for the WDT prescaler actually oscillator which does not require any external a postscaler but shared with the Timer0 prescaler may components.

If the device is in Sleep mode, a WDT time-out causes the device to 2: The TO bit in the Status register the prescaler count will be cleared but the will be cleared upon a Watchdog Timer time-out.

Shaded cells are not used by the Watchdog Timer. See Register for operation of these bits. For the device to Power-down mode is entered by executing a SLEEP wake-up through an interrupt event, the corresponding instruction. If the GIE bit is turned off. Watchdog Timer wake-up if WDT was enabled. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. CCP Capture mode interrupt.

Special event trigger Timer1 in Asynchronous mode using an external clock. Comparator output changes state. Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. This delay will not be there for RC Oscillator mode.TABLE There are two timers that offer necessary delays on power-up. Is there any incorrect or misleading information what and where? Interrupt is generated once the Stop condition is complete. On the detection of The receiver block diagram is shown in Figure

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